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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1996 feb 16 integrated circuits SAA9750H camera digital signal processor (camdsp)
1996 feb 16 2 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H features y/c separator for mosaic filter colour ccd which can be used with pal or ntsc ccds with horizontal resolution of 510, 670, 720 or 768 pixels line sequential colour processing (r - y) and (b - y) 9 bit input signal (the internal processing is 10-bit) digital feedback clamp control for y/c separation two 768 9 line memories for y/c separation aperture correction using phase linear filters coring of low level signals to reduce noise colour encoder in accordance with the pal or ntsc system. colour subcarrier is made by a discrete time oscillator (dto) operating on system clock slew rate controlled outputs for reduction of digital noise rgb inputs for title mix high accuracy 8 bit dac outputs for luminance and chrominance signals sync signal generator (ssg) to generate all necessary timing signals serial interface for microprocessor control of camdsp settings y and c signals accessible to incorporate digital features including digital feature functions (mosaic, sepia, solarization, slice and negative/positive inversion). general description the camera digital signal processor (camdsp) is intended for use with a mosaic filter colour ccd. the ic generates luminance and chrominance signals from the ccd signal. the device consists of a luminance and colour separator employing two 768 9 line memories, a pal/ntsc encoder, a dual 8-bit video dac, a sync signal generator (ssg) and a simple serial interface to control many settings. quick reference data ordering information symbol parameter min. typ. max. unit v dda1 y-dac analog supply voltage (pin 1) 2.7 3.0 3.3 v v dda2 c-dac analog supply voltage (pin 2) 2.7 3.0 3.3 v v ddd1 digital supply voltage (pin 41) 2.7 3.0 3.3 v v ddd2 digital supply voltage (pin 53) 2.7 3.0 3.3 v v ddd3 digital supply voltage (pin 65) 2.7 3.0 3.3 v v ih high level digital input voltage 0.7v ddd - v ddd v v il low level digital input voltage 0 - 0.3v ddd v v oh high level digital output voltage v ddd - 0.5 -- v v ol low level digital output voltage -- 0.5 v t amb operating ambient temperature - 20 - +70 c type number package name description version SAA9750H lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm sot315-1
1996 feb 16 3 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H block diagram handbook, full pagewidth microprocessor interface y processing c processing fifo 768 9 fifo 768 9 clamp x0h y settings clamp settings c settings x1h x2h title switch encoder delay y enc sync 12 to 19 43 to 50 title mix uv enc title mix sync signal generator 30 62 cpob clamp cs ck di vrst hrst clk1 clk2 csync hd fld synci v ssa1 v ssa2 y 0 to y 7 test1 test2 vd cp2 hsync 61 9 68 to 76 59 clock 55 77 6 56 63 57 58 8 8 29 20 8 9 10 11 7 1 2 a d 21 to 28 33 to 40 encoder settings ssg settings 31 32 51 52 66 67 + 8 8 8 a d 8 479 80 y enc7 to y enc0 uv enc0 to uv enc7 3 78 v refy v refc y out c out v dda2 v dda1 v ddd1 v ddd3 v ddd2 uv sel lsw tsw wclip uv 0 to uv 7 cds 0 to cds 8 b g r mha302 5 60 41 53 65 SAA9750H v ssd2 64 v ssd3 54 v ssd1 42 fig.1 block diagram.
1996 feb 16 4 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H pinning symbol pin input/output analog/digital description v dda1 1 supply - analog supply voltage 1 for y-dac v dda2 2 supply - analog supply voltage 2 for c-dac c out 3 output analog c-dac output v ssa1 4 supply - analog ground 1 for c-dac v refc 5 -- c-dac decoupling voltage test2 6 input digital test 2 pin lsw 7 input digital line switch for secam tsw 8 input digital title memory switch r 9 input digital title memory colour (red) g 10 input digital title memory colour (green) b 11 input digital title memory colour (blue) uv enc0 12 input digital b - y and r - y signal to encoder (lsb) uv enc1 13 input digital b - y and r - y signal to encoder uv enc2 14 input digital b - y and r - y signal to encoder uv enc3 15 input digital b - y and r - y signal to encoder uv enc4 16 input digital b - y and r - y signal to encoder uv enc5 17 input digital b - y and r - y signal to encoder uv enc6 18 input digital b - y and r - y signal to encoder uv enc7 19 input digital b - y and r - y signal to encoder (msb) wclip 20 output digital white-clip uv 7 21 output digital time multiplexed b - y and r - y (msb) uv 6 22 output digital time multiplexed b - y and r - y uv 5 23 output digital time multiplexed b - y and r - y uv 4 24 output digital time multiplexed b - y and r - y uv 3 25 output digital time multiplexed b - y and r - y uv 2 26 output digital time multiplexed b - y and r - y uv 1 27 output digital time multiplexed b - y and r - y uv 0 28 output digital time multiplexed b - y and r - y (lsb) uv sel 29 output digital b - y or r - y active at uv output cs 30 input digital microprocessor interface (chip select) ck 31 input digital microprocessor interface (clock) di 32 input digital microprocessor interface (data input) y 0 33 output digital luminance signal (lsb) y 1 34 output digital luminance signal y 2 35 output digital luminance signal y 3 36 output digital luminance signal y 4 37 output digital luminance signal y 5 38 output digital luminance signal y 6 39 output digital luminance signal y 7 40 output digital luminance signal (msb)
1996 feb 16 5 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H v ddd1 41 supply - digital supply voltage 1 v ssd1 42 supply - digital ground 1 y enc7 43 input digital luminance signal to encoder (msb) y enc6 44 input digital luminance signal to encoder y enc5 45 input digital luminance signal to encoder y enc4 46 input digital luminance signal to encoder y enc3 47 input digital luminance signal to encoder y enc2 48 input digital luminance signal to encoder y enc1 49 input digital luminance signal to encoder y enc0 50 input digital luminance signal to encoder (lsb) vrst 51 input digital external vd (vertical drive) hrst 52 input digital external hd (horizontal drive) v ddd3 53 supply - digital supply voltage 3 v ssd3 54 supply - digital ground 3 vd 55 output digital vd timing for ppg ic hd 56 output digital hd timing for ppg ic fld 57 output digital ?eld pulse output hsync 58 output digital horizontal timing for yc processing csync 59 output digital composite sync pulse synci 60 input digital sync input for bypass mode clamp 61 output (3-state) digital clamp voltage control cpob 62 input digital optical black pulse cp2 63 output digital clamping pulse v ssd2 64 supply - digital ground 2 v ddd2 65 supply - digital supply voltage 2 clk1 66 input digital clock 1 clk2 67 input digital clock 2 cds 0 68 input digital cds signal (lsb) cds 1 69 input digital cds signal cds 2 70 input digital cds signal cds 3 71 input digital cds signal cds 4 72 input digital cds signal cds 5 73 input digital cds signal cds 6 74 input digital cds signal cds 7 75 input digital cds signal cds 8 76 input digital cds signal (msb) test1 77 input digital test 1 pin v refy 78 -- y-dac decoupling voltage v ssa2 79 supply - analog ground 2 for y-dac y out 80 output analog y-dac output symbol pin input/output analog/digital description
1996 feb 16 6 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H fig.2 pin configuration. handbook, full pagewidth SAA9750H mha301 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v dda1 v dda2 c out v ssa1 v refc test2 lsw tsw r g b uv enc0 uv enc1 uv enc2 uv enc3 uv enc4 uv enc5 uv enc6 uv enc7 wclip synci csync hsync fld hd vd v ssd3 v ddd3 hrst vrst y enc0 y enc1 y enc2 y enc3 y enc4 y enc5 y enc6 y enc7 v ssd1 v ddd1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 uv 7 uv 6 uv 5 uv 4 uv 3 uv 2 uv 1 uv 0 uv sel cs ck di y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y out v ssa2 v refy test1 cds 8 cds 7 cds 6 cds 5 cds 4 cds 3 cds 2 cds 1 cds 0 clk2 clk1 v ddd2 v ssd2 cp2 cpob clamp 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1996 feb 16 7 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H functional description the camera digital signal processor (camdsp) is intended for use with a mosaic filter colour ccd. the input signal is an 8-bit or 9-bit digitized ccd signal. after agc and gamma correction, clamping of the input signal is achieved by feedback clamp level control. in the luminance processing, symmetrical horizontal and vertical aperture correction are carried out. coring is also carried out to reduce noise at low signal levels. in the chrominance processing, white balance control and matrix control is adjustable. a false colour correction circuit reduces aliasing of high frequency input signals. a white-clip makes the colour white at highlights. in the encoder part, the colour encoder subcarrier is made by the discrete time oscillator thus eliminating the use of an extra crystal. the subcarrier frequency for pal or ntsc is selectable. the encoding can be in pal or ntsc format. the encoded signal is output via separate 8-bit digital-to-analog converters (dacs) for luminance and chrominance. in the event of secam the output is a line sequential - (r - y)/(b - y) signal. a line memory interface allows for mixing of rgb signals in the main signal. the encoder can be bypassed completely, in this event only the title mix is carried out before digital-to-analog conversion. the ssg generates all necessary timing signals. timing signals for external devices ntsc, pal and secam are also made. the ssg can be locked to an external video source. camdsp can operate with 510h, 670h, 720h and 768h colour mosaic ccds both pal and ntsc type. in the 510h ccd application the upsampling clock is used for the encoder part, therefore two clock frequencies (f s and 2f s ) are required. limiting values in accordance with the absolute maximum rating system (iec 134). note 1. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor. thermal characteristics symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +5.0 v v dda analog supply voltage - 0.5 +5.0 v p tot total power dissipation - 500 mw v i digital input voltage - 0.5 v ddd + 0.5 v v o digital output voltage - 0.5 v ddd + 0.5 v t stg storage temperature - 65 +150 c t amb operating ambient temperature - 20 +70 c v es electrostatic handling note 1 - 2000 +2000 v i latch latch-up protection current 100 - ma symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 57 k/w
1996 feb 16 8 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H dc characteristics v dd = 2.7 to 3.3 v; t amb = - 20 to +70 c; unless otherwise speci?ed. note 1. 510h pal; v dd = 3 v; dac r l =2k w . dac characteristics v dd = 3.0 v; t amb = +25 c; r l = open-circuit; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit i dd supply current note 1 - 60 150 ma inputs: lsw, tsw, r, g, b, uv enc0 to uv enc7 , cs, ck, di, y enc0 to y enc7 , vrst, hrst, synci, cpob, clk1, clk2, cds 0 to cds 7 , test1 and test2 v ih high level input voltage 0.7v dd -- v v il low level input voltage -- 0.3v dd v i ih high level input current v ih =v dd -- 1 m a i il low level input current v il =v ss --- 1 m a outputs: wclip, uv 0 to uv 7 , uv sel , y 0 to y 7 , vd, hd, fld, hsync, csync and cp2 v oh high level output voltage i oh = - 20 m av dd - 0.1 -- v i oh = - 2ma v dd - 0.5 -- v v ol low level output voltage i ol = +20 m a -- 0.1 v i ol =+2ma -- 0.5 v output: clamp (3-state output) v oh high level output voltage i oh = - 20 m av dd - 0.1 -- v i oh = - 8ma v dd - 0.5 -- v v ol low level output voltage i ol = +20 m a -- 0.1 v i ol =+8ma -- 0.5 v i tl 3-state leakage current v ih =v dd ; v il =v ss -- 5 m a symbol parameter min. typ. max. unit outputs: y out and c out f cmax conversion frequency speed 20 -- mhz inl dc integral linearity error - 0.5 - +0.5 lsb dnl dc differential linearity error - 0.5 - +0.5 lsb v o(p-p) full scale output except sync (peak-to-peak value) 1.61 1.66 1.72 v r o internal series output resistance - 75 -w
1996 feb 16 9 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H ac characteristics microprocessor interface v dd = 2.7 to 3.3 v; v il =0v; v ih =v dd ; v ref = 0.5v dd ; t amb = - 20 to +70 c; input t r and t f = 30 ns; unless otherwise speci?ed. symbol parameter min. typ. max. unit t css cs set-up time 0.4 --m s t csh cs hold time 0.4 --m s t csd cs deselection time 0.2 --m s t ds di set-up time 0.4 --m s t dh di hold time 0.4 --m s f ck ck frequency -- 0.5 mhz t wckh high level pulse width of ck 1.0 --m s t wckl low level pulse width of ck 1.0 --m s t r rise time of ck -- 100 ns t f fall time of ck -- 100 ns fig.3 microprocessor interface timing. cs ck di t css t r t f mha305 t csd v ref v ref v ref v ih v ih v ih v il v il v il t csh t wckh 90% 90% 10% 10% t ds t dh t wckl
1996 feb 16 10 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H data input/output timing (clk1 and clk2) v dd = 2.7 to 3.3 v; v il =0v; v ih =v dd ; v ref = 0.5v dd ;t amb = - 20 to +70 c; t r and t f = 6 ns; output load capacitance = 20 pf; unless otherwise speci?ed. notes 1. data inputs: synci, cpob, cds 0 to cds 8 , vrst, hrst, r, g, b, tsw, y enc0 to y enc7 , lsw and uv enc0 to uv enc7 . 2. data outputs: uv sel , uv 0 to uv 7 , y 0 to y 7 , wclip, csync, hsync, fld, hd, vd and cp2. 3. t amb = +25 c; v dd = 3.0 v. symbol parameter conditions min. typ. max. unit t dis data input set-up time note 1 5 -- ns t dih data input hold time note 1 8 -- ns t dod data output delay time notes 2 and 3 -- 50 ns t doh data output hold time notes 2 and 3 -- 50 ns t duty duty factor of clk1 and clk2 - 50 - % fig.4 data input/output timing (clk1 and clk2). clk1 and clk2 data inputs data outputs t f mha306 t r v ref v ih v ih v oh v il v il v ol 90% 10% 90% 10% 90% 10% 90% 10% 90% 10% 90% 10% t dis t dod t dih t doh
1996 feb 16 11 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H ssg timing clock count for ntsc and pal mode fig.5 ssg timing (continued in fig.6). handbook, full pagewidth ccd 510h 1h 606 (618) clocks 596 (603) 1h 806 (824) clocks 0 50 (45) 60 (60) 24 (24) 33 (33) 48 (48) 57 (57) 62 (62) 80 (80) 80 (80) 32 (32) 28 (28) 48 (48) 51 (51) 61 (61) 100 (100) 108 (108) 121 (121) mha307 168 (184) 195 (203) 107 (107) 165 (177) 93 (93) 139 (151) 75 (75) ccd 670h 0 shd hd cp2 y 0 to y 7 hsync yda and cda sync shd hd cp2 y 0 to y 7 hsync yda and cda sync - 10 ( - 15)
1996 feb 16 12 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H shd: hd output can be changed by microprocessor to shd outputs. hd: for timing of input cds signal for ppg ic. hsync: for output luminance signal y7 to y0 and chrominance signal uv7 to uv0 of camdsps yc processing. sync: composite sync pulse of dacs output. output of csync (pin 59): sync + 1 clock (see figs 5 and 6). fig.6 ssg timing (continued from fig.5). handbook, full pagewidth ccd 720h 1h 858 (864) clocks 1h 910 (908) clocks 0 83 (83) 83 (83) 36 (36) 34 (34) 50 (50) 63 (63) 67 (67) 89 (89) 89 (89) 36 (36) 33 (33) 54 (54) 65 (63) 71 (71) 108 (108) 121 (121) 138 (138) mha308 191 (203) 223 (235) 130 (130) 209 (229) 113 (113) 172 (182) 104 (104) ccd 768h 0 shd hd cp2 y 0 to y 7 hsync yda and cda sync shd hd cp2 y 0 to y 7 hsync yda and cda sync
1996 feb 16 13 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H clock table 1 clock frequency table 2 clock used for each block microprocessor interface format mode ccd clk1 (mhz) clk2 (mhz) ntsc 510h 9.5350 19.0699 670h 12.7132 - 720h 13.5000 - 768h 14.3182 - pal secam 510h 9.6563 19.3125 670h 12.8750 - 720h 13.5000 - 768h 14.1875 - mode ssg block y/c block encoder block y-dac block c-dac block 510h ntsc/pal clk1 clk1 clk1 and clk2 (upsampling) clk1 clk2 other modes clk1 clk1 clk1 clk1 clk1 fig.7 microprocessor interface format. (1) slave address 001. handbook, full pagewidth cs ck di msb lsb msb lsb msb lsb data subaddress slave address (1) mha304
1996 feb 16 14 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H table 3 microprocessor interface format function subaddress data msb lsb field delay 00000 x ------ fd title enable 00000 x ----- te - title polarity 00000 x ---- tp -- false colour +6 db 00000 x --- fcu --- uv +6 db 00000 x -- cup ---- y +6 db 00000 x - yup ----- y clear 00000 x ycl ------ hap low clip 00001 x x ha5 ha4 ha3 ha2 ha1 ha0 vap low clip 00010 x x va5 va4 va3 va2 va1 va0 ap high clip 00011 x --- ap3 ap2 ap1 ap0 ap gain 00011 x ag2 ag1 ag0 ---- y gain 00100 x x yg5 yg4 yg3 yg2 yg1 yg0 y pedestal 00101 yp7 yp6 yp5 yp4 yp3 yp2 yp1 yp0 slice 00110 x x x --- sli snp mosaic 00110 x x x mos px1 px0 -- slice level 00111 sll7 sll6 sll5 sll4 sll3 sll2 sll1 sll0 subcarrier 01000 s7 s6 s5 s4 s3 s2 s1 s0 01001 s15 s14 s13 s12 s11 s10 s9 s8 01010 ---- s19 s18 s17 s16 uv polarity 01010 --- uvp ---- synci 01010 -- syn ----- encoder mode 01010 em1 em0 ------ burst level 01011 x bl6 bl5 bl4 bl3 bl2 bl1 bl0 hrst delay 01101 d7 d6 d5 d4 d3 d2 d1 d0 01110 ------ d9 d8 ccd type 01110 ---- h1 h0 -- 525/625 line 01110 --- ll ---- master/slave 01110 -- ms ----- adc delay 01110 ad1 ad0 ------ solarization 01111 x x x --- tr1 tr0 01111 x x x -- sol -- sepia 01111 x x x - sep --- negative/positive 01111 x x x np ---- r gain 10000 x rg6 rg5 rg4 rg3 rg2 rg1 rg0 b gain 10001 x bg6 bg5 bg4 bg3 bg2 bg1 bg0 u gain 10010 x x ugp5 ugp4 ugp3 ugp2 ugp1 ugp0 10011 x x ugn5 ugn4 ugn3 ugn2 ugn1 ugn0
1996 feb 16 15 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H table 4 explanation of functions of table 3 v gain 10100 x x vgp5 vgp4 vgp3 vgp2 vgp1 vgp0 10101 x x vgn5 vgn4 vgn3 vgn2 vgn1 vgn0 u matrix 1 gain 10110 x x um5 um4 um3 um2 um1 um0 u matrix 2 gain 10111 x x un5 un4 un3 un2 un1 un0 v matrix 1 gain 11000 x x vm5 vm4 vm3 vm2 vm1 vm0 v matrix 2 gain 11001 x x vn5 vn4 vn3 vn2 vn1 vn0 sp polarity 11010 x x x ---- spp fh2 polarity 11010 x x x --- fhp - colour ?lter 11010 x x x -- lpf -- hd, vd polarity 11010 x x x - shv --- sub lpf 11010 x x x jgm ---- false colour 11011 th7 th6 th5 th4 th3 th2 th1 th0 white-clip level 11100 wc7 wc6 wc5 wc4 wc3 wc2 wc1 wc0 y delay 11101 x x x x -- ydl1 ydl0 c delay 11101 x x x x cdl1 cdl0 -- symbol description fd field delay control te title enable control tp title polarity control fcu false colour plus 6 db up cup uv +6 db up yup y gain +6 db up ycl y clear control ha0 to ha5 horizontal aperture low clip level control va0 to va5 vertical aperture low clip level control ap0 to ap3 aperture high clip level control ag0 to ag2 aperture gain control yg0 to yg5 y gain control yp0 to yp7 y pedestal control snp slice effect polarity sli slice on/off px0 and px1 mosaic effect pixels control mos mosaic on/off sll0 to sll7 slice level control s0 to s19 subcarrier control uvp uv sel polarity control syn sync signal selection function subaddress data msb lsb
1996 feb 16 16 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H em0 and em1 encoder mode control bl0 to bl6 burst level control d0 to d9 hrst and vrst preset control h0 and h1 ccd type selection ll 525/625 line control ms master/slave control ad0 and ad1 adc delay control tr0 and tr1 solarization effect control sol solarization on/off sep sepia on/off np negative/positive on/off rg0 to rg6 red gain control bg0 to bg6 blue gain control ugp0 to ugp5 u gain control for positive side ugn0 to ugn5 u gain control for negative side vgp0 to vgp5 v gain control for positive side vgn0 to vgn5 v gain control for negative side um0 to um5 u matrix 1 gain control un0 to un5 u matrix 2 gain control vm0 to vm5 v matrix 1 gain control vn0 to vn5 v matrix 2 gain control spp sp polarity control fhp fh2 polarity control lpf colour filter control shv hd and vd polarity control jgm sub lpf control for false colour th0 to th7 threshold control for false colour suppression wc0 to wc7 white-clip level control ydl0 and ydl1 y delay control cdl0 and cdl1 c delay control symbol description
1996 feb 16 17 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H microprocessor setting table 5 field delay control table 6 title enable control table 7 title polarity control table 8 false colour +6 db up table 9 uv +6 db up table 10 y gain +6 db up table 11 y clear control field delay control fd normal 0 one ?eld delay 1 title enable control te title insertion off 0 title insertion on 1 title polarity control tp negative 0 positive 1 false colour +6 db up fcu 0 db gain 0 +6 db gain 1 uv +6 db up cup 0 db gain 0 +6 db gain 1 y gain +6 db up yup 0 db gain 0 +6 db gain 1 y clear control ycl normal 0 clear 1 horizontal aperture low clip level control = ha5 to ha0. vertical aperture low clip level control = va5 to va0. aperture high clip level control = ap3 to ap0. aperture gain control y gain control y pedestal level control = yp7 to yp0. table 12 slice effect polarity table 13 slice on/off table 14 mosaic effect pixels control table 15 mosaic on/off slice level control = sll7 to sll0. subcarrier frequency control slice effect polarity snp negative 0 positive 1 slice on/off sli off normal 0 on slice 1 mosaic effect pixels control px1 px0 4 4 pixels 0 0 8 8 pixels 0 1 16 16 pixels 1 0 32 32 pixels 1 1 mosaic on/off mos off normal 0 on mosaic 1 ag 2:0 [] 8 ------------------------ = yg 5:0 [] 32 ------------------------ - = s19:0 [] f encoder 1048576 ------------------------------------------------- =
1996 feb 16 18 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H table 16 uv sel polarity control table 17 sync signal selection table 18 encoder mode control burst level control (of full-scale dac output). hrst and vrst preset control = d9 to d0, preset horizontal counter to count d9 to d0. table 19 ccd type selection table 20 525/625 line control uv sel polarity control uvp normal 0 high: u(b - y) low: v(r - y) invert 1 high: v(r - y) low: u(b - y) sync signal selection syn internal sync 0 external sync (from synci pin 60) 1 encoder mode control em1 em0 pal 0 0 ntsc 0 1 secam 1 0 bypass 1 1 ccd type selection h1 h0 510h 0 0 670h 0 1 720h 1 0 768h 1 1 525/625 line control ll 525 line 0 625 line 1 bl 6:0 [] 128 ---------------------- - = table 21 master/slave control table 22 ad converter delay control table 23 solarization effect control table 24 solarization on/off table 25 sepia on/off table 26 negative/positive on/off master/slave control ms master 0 slave 1 adc delay control (camdsp delay) ad1 ad0 3ts 0 0 4ts 0 1 5ts 1 0 6ts 1 1 solarization effect control (slice of bits) tr1 tr0 3 bits (lsb) 0 0 4 bits (lsb) 0 1 5 bits (lsb) 1 0 6 bits (lsb) 1 1 solarization on/off sol normal 0 solarization on 1 sepia on/off sep normal 0 sepia on 1 negative/positive on/off np normal 1 negative 0
1996 feb 16 19 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H r channel gain control = 1 + (1) b channel gain contro l=1+ (1) u gain control for positive side u gain control for negative side v gain control for positive side v gain control for negative side u matrix 1 gain control (1) u matrix 2 gain control (1) v matrix 1 gain control (1) v matrix 2 gain control (1) table 27 sp polarity control table 28 fh2 polarity control (1) rg, bg, um, un, vm and vn are twos complement. sp polarity control spp normal 0 h: ye + mg or ye + gr l: cy + gr or cy + mg invert 1 h: cy + gr or cy + mg l: ye + mg or ye + gr fh2 polarity control fhp normal 0 h: 2b-g l: 2r-g invert 1 h: 2r-g l: 2b-g rg 6:0 [] 128 ------------------------ - bg 6:0 [] 128 ------------------------ ugp 5:0 [] 16 ----------------------------- = ugn 5:0 [] 16 ----------------------------- = vgp 5:0 [] 16 ---------------------------- - = vgn 5:0 [] 16 ----------------------------- = um 5:0 [] 32 ------------------------ - = un 5:0 [] 32 ------------------------ = vm 5:0 [] 32 ------------------------ - = vn 5:0 [] 32 ----------------------- - = table 29 colour ?lter control table 30 hd and vd polarity control table 31 sub lpf control for false colour threshold control for false colour suppress = th7 to th0. white clip level control = 2 wc7 to wc0. table 32 y delay control table 33 c delay control colour filter control lpf lpf1 0 [1,1,3,3,4,4,4,4,3,3,1,1]/32 lpf2 1 [ - 1,0,4,8,10,8,4,0, - 1]/32 hd and vd polarity control shv normal 0 invert 1 sub lpf control for false colour jgm normal 0 sub lpf 1 y delay control ydl1 ydl0 0 clock period 0 0 +1 clock period 0 1 +2 clock periods 1 0 +3 clock periods 1 1 c delay control cdl1 cdl0 0 clock period 0 0 +1 clock period 0 1 +2 clock periods 1 0 +3 clock periods 1 1
1996 feb 16 20 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H camera fig.8 camera block diagram (SAA9750H and saa9740h). handbook, full pagewidth camdsp signal processor y/c separation ssg encoder SAA9750H adc iris driver dac ppg iris agc ccd high speed shuffle control lpf camera adc i/f(8) cds(8) uv(8) y(5) bpf y mha303 c y (8-bit) uv (8-bit) cds agc, gamma clamp hd/vd 8-bit SAA9750H micro- processor serial data bus a2cf af/ae/awb uv sel hsync wclip motor driver focus lens motor driver zoom lens hall sensor focus sensor zoom encoder 3
1996 feb 16 21 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 97-07-15 95-12-19 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
1996 feb 16 22 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 feb 16 23 philips semiconductors preliminary speci?cation camera digital signal processor (camdsp) SAA9750H definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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(63) 2 816 6380, fax. (63) 2 817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scds47 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 537021/1100/01/pp24 date of release: 1996 feb 16 document order number: 9397 750 00641

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